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mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.1 overview 1.1.1 overview the mn101e series of 8-bit single-chip microcompu ters (the memory expansion version of mn101c series) incorporate mu ltiple types of peripheral functions. this chip series is well suited for camera, vcr, md, tv, cd, ld, printer, telephone, home autom ation, pager, air conditioner, ppc, fax machine, music instrument and other applications. this lsi brings to embedded microcomputer applicat ions flexible, optimized hardware configurations and a simple efficient instruction set. the mn101e30 series have an internal 928 kb (maximum) of rom and 8 kb (maximum) of ram. peripheral functions include 6 external interrupts, 30 internal inter- rupts including nmi, 9 timer counters, 6 sets of seri al interfaces, a/d converter, d/a converter, lcd driver, watchdog timer, 2 sets of automatic data tr ansfer, synchronous output function and buzzer out- put. the configuration of this microcomputer is well suited for application as a system controller in cam- era, timer selector for vcr, cd player, or minicomp onent, and also suited for audio reproduction with a high-precision d/a converter. with three oscillation system (hig h frequency: max. 20 mhz / low frequency: 32.768 khz and pll: fre- quency multiplier of high frequency) contained on th e chip, the system clock can be switched to high frequency input (high speed mode), pll input (pll mode), or to low frequency input (low speed mode). the system clock is generat ed by dividing the oscillation clock. th e best operation clock for the system can be selected by switching its frequency by software. high speed mode has the normal mode based on fpll/2 which is half cl ock generated from an orig inal oscillation and pll, and the double speed mode based on fpll which is clock generated fr om an original oscillation without dividing. a machine cycle (min. instructions execution) in the normal mode is 100 ns when fosc is 20 mhz (at the time that pll is not used). a machine cycle in the do uble speed mode is 50 ns when fosc is 20 mhz. a machine cycle in the pll mode is 50 ns (maximum).the package is 100-pin qfp, lqfp.
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.1.2 product summary this manual describes the following models of the mn 101e30 series. these products have identical functions, and their memory capacity and type are shown below. table:1.1.1 product summary .. this manual is described with a focus on mn101e30n. .. model rom size ram size classification package mn101e30n 508 kb 8 kb mask rom version lqfp100-p-1414c qfp100-p-1818b mn101e30r 928 kb 8 kb mask rom version qfp100-p-1818b MN101EF30R 928 kb 8 kb flash eeprom version lqfp100-p-1414 qfp100-p-1818b
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.2 hardware functions ? feature - rom capacity: 508/928 kb - ram capacity: 8 kb - package: 100pin lqfp (14 mm square, 0.5 mm pitch) 100pin qfp (18 mm square, 0.65 mm pitch) - machine cycle: high speed mode 0.05 ms/ 20 mhz (2.2 v to 5.5 v) pll mode 0.05 ? s/ 20 mhz (2.2 v to 5.5 v) low speed mode 62.5 ? s/16 khz (2.2 v to 5.5 v) - clock gear: operation speed of system cl ock is variable by changing the frequency. - multiplied clock: high-speed frequency clock (fosc) can be multiplied by 2, 3, 4, 5, 6, 8 and 10. - memory bank: data memory space is expanded by the bank system. - bank for the source address/ba nk for the destination address. - rom correction: correcting address designation: up to 7 addresses possible - operation modes: normal mode ( high speed mode) pll mode slow mode ( low speed mode) halt mode stop mode (the operation clock can be switched in each mode.) - operating voltage: 2.2 v to 5.5 v
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e - operating temperature: -40 ? c to +85 ? c - interrupt: 36 levels - nmi-watchdog timer overflow - tm0irq-timer 0 interrupt (8-bit timer) - tm1irq-timer 1 interrupt (8-bit timer) - tm2irq-timer 2 interrupt (8-bit timer) - tm3irq-timer 3 interrupt (8-bit timer) - tm4irq-timer 4 interrupt (8-bit timer) - tm6irq-timer 6 interrupt (8-bit timer) - tbirq-clock timer interrupt - tm7irq-timer 7 interrupt (16-bit timer) - t7oc2irq- timer 7 interrupt (16-bit timer) - tm8irq-timer 8 interrupt (16-bit timer) - t8oc2irq- timer 8 interrupt (16-bit timer) - tm9irq-timer 9 interrupt (16-bit timer) - t9oc2irq- timer 9 interrupt (16-bit timer) - sc0tirq-serial interface 0 interrupt - sc0rirq-serial interface 0 uart reception inte rrupt (peripheral func tion group interrupt) - sc1tirq-serial interface 1 interrupt - sc1rirq-serial interface 1 uart reception inte rrupt (peripheral func tion group interrupt) - sc2tirq-serial interface 2 interrupt - sc2rirq-serial interface 2 uart reception interrupt - sc3tirq-serial interface 3 interrupt - sc3rirq-serial interface 3 uart reception inte rrupt (peripheral func tion group interrupt) - sc4tirq- serial interface 4 interrupt - sc4sirq- serial interface 4 stop condition interrupt (peripheral function group interrupt) - sc5tirq- serial interface 5 interrupt (peripheral function group interrupt)
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e - adirq-ad conversion end (peripheral function group interrupt) - atc0irq-atc0 interrupt (perip heral function group interrupt) - atc1irq-atc1 interrupt (perip heral function group interrupt) edge selectable - irq0:external interrupt (ac zero-cross detector, with/without noise filter) - irq1:external interrupt (ac zero-cross detector, with/without noise filter) - irq2:external interrupt (both edges interrupt) - irq3:external interrupt (both edges interrupt) - irq4:external interrupt (both edges interrupt) - irq5:external interrupt (key scan interrupt only)

MN101EF30R) mode object microcontroller activation area pin setting register setting nrst atrst dmod p01 p02 mmod exmem flag single chip mode flash-rom mask-rom main (1) l or h h normal pin l 0 memory ex tend mode flash-rom mask-rom main (1) l or h h normal pin l 1 micro controller rewriting mode (3) flash-rom boot (1) l h normal pin h 0 d-wire communication mode(3) flash-rom - (2) l (2) pull up(2) pull up(2) l 0 p41 / seg34 / sbi3b / rxd3b p40 / seg35 / sbo3b / txd3b p36 / seg36 p35 / seg37 / sbi4b p34 / seg38 / sbt4b / scl4b p33 / seg39 / sbo4b / sda4b p32 / seg40 / sbt2b p31 / seg41 / sbi2b / rxd2b p30 / seg42 / sbo2b / txd2b p16 / seg43 / tm8ioc / nbuzzer b p15 / seg44 / tm7ioc / buzzerb p14 / seg45 / tm4ioc p13 / seg46 / tm3ioc p12 / seg47 / tm1ioc p11 / seg48 / tm2ioc p10 / seg49 / tm0ioc / rmoutc p24 / seg50 / irq4 p23 / seg51 / irq3 p22 / seg52 / irq2 p21 / seg53 / irq1 / acz1 p20 / seg54 / irq0/ acz0 p07 / led7 / da_a p06 / led6 / sbt3a p05 / led5 / sbi3a / rxd3a p04 / led4 / sbo3a / txd3a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 rmouta / tm0ioa / an0 / pa0 tm1ioa / an1 / pa1 tm2ioa / an2 / pa2 tm3ioa / an3 / pa3 tm4ioa / an4 / pa4 tm7ioa / an5 / pa5 tm8ioa / an6 / pa6 tm9ioa / an7 / pa7 vref+ mmod atrst nrst / p27 xo / p91 xi / p90 vss osc1 osc2 vdd5 vdd18 (1.8 v capacity) * vdd(3.3 v capacity) dmod rxd1a / sbi1a / tm7iob / led0 / p00 txd1a / sbo1a / tm8iob / led1 / p01 sbt1a / tm9iob / led2 / p02 rmoutb / tm0iob / tm2iob / led3 / p03 p72 / seg9 / nwe / sbt2a p71 / seg10 / a7 / sbi2a / rxd2a p70 / seg11 / a6 / sbo2a / txd2a p67 / seg12 / a5 / sbt4a / scl4a p66 / seg13 / a4 / sbo4a / sda4a p65 / seg14 / a3 / sbi4a p64 / seg15 / a2 / tm4iob p63 / seg16 / a1 / tm3iob p62 / seg17 / a0 / tm1iob p61 / seg18 / da_b p60 / seg19 p50 / seg20 / key0 / d0 / sbo0a / txd0a p51 / seg21 / key1 / d1 / sbi0a / rxd0a p52 / seg22 / key2 / d2 / sbt0a p53 / seg23 / key3 / d3 / buzzera p54 / seg24 / key4 / d4 / nbuzzera p55 / seg25 / key5 / d5 p56 / seg26 / key6 / d6 p57 / seg27 / key7 / d7 p47 / seg28 / scl5b p46 / seg29 / sda5b p45 / seg30 / sbt0b p44 / seg31 / sbi0b / rxd0b p43 / seg32 / sbo0b / txd0b p42 / seg33 / sbt3b sda5a / nre / seg8 / p73 scl5a / ncs / seg7 / p74 txd1b / sbo1b / a8 / seg6 / p75 rxd1b / sbi1b / a9 / seg5 / p76 sbt1b / a10 / seg4 / p77 tm9od0 / sdo0 / a11 / seg3 / p80 tm9od1 / sdo1 / a12 / seg2 / p81 tm9od2 / sdo2 / a13 / seg1 / p82 tm9od3 / sdo3 / a14 / seg0 / p83 tm9od4 / sdo4 / a15 / com0 / p84 tm9od5 / sdo5 / a16 / com1 / p85 sdo6 / a17 / com2 / p86 sdo7 / a18 / com3 / p87 a19 / vlc3 / p92 ndk / vlc2 / p93 da_c / vlc1 / p94 da_d / p95 avdd dai-dout dai-aout avss an11 / pb3 an10 / pb2 an9 / pb1 an8 / pb0 mn101e30n/e30r/ef30r 100 pin qfp/lqfp (top view) * n.c. (non-connection pin) in mask rom version
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.3.2 pin specification table:1.3.1 pin specification (1)the mode becomes fixed from the pin state in releasing nrst(l to h). (2)this is controlled by a dedicated on-board programmer (3)this mode becomes the rewriting mode only for flash microcontroller. therefore does not exist in the mask version (mn101e30n/e30r) pins special functions i/o direction control pin control functions description p00 rxd1a sbi1a in/out p0dir0 p0plu0 rxd1a: uart1 reception data input sbi1a: serial1 reception data out- put tm7iob led0 tm7iob: timer 7 input / output led0: led driver pin 0 p01 txd1a sbo1a in/out p0dir1 p0plud1 txd1a: uart1 transmission data output sbo1a: serial1 transmission data output tm8iob led1 tm8iob: timer 8 input / output led1: led driving pin 1 p02 sbt1a tm9iob in/out p0dir2 p0plud2 sbt1a: serial 1 clock input / output tm9iob: timer 9 input / output led2 led2: led driving pin 2 p03 rmoutb tm0iob in/out p0dir3 p0plud3 rmoutb: remote control carrier output tm0iob: timer 0 input / output tm2iob led3 tm2iob: timer 2 input / output led3: led driving pin 3 p04 led4 sbo3a in/out p0dir4 p0plud4 led4: led driving pin 4 sbo3a: serial3 transmission data output txd3a txd3a: uart3 transmission data output p05 led5 sbi3a in/out p0dir5 p0plud5 led5: led driving pin 5 sbi3a: serial3 reception data out- put rxd3a rxd3a: uart3 reception data input p06 led6 sbt3a in/out p0dir6 p0plud6 led6: led driving pin 6 sbt3a: serial3 clock input / output p07 led7 da_a in/out p0dir7 p0plud7 led7: led driving pin 7 da_a: analog a output p10 seg49 tm0ioc in/out p1dir0 p1plud0 seg49: segment49 output tm0ioc: timer0 input / output rmoutc rmoutc: remote control carrier output p11 seg48 tm2ioc in/out p1dir1 p1plud1 seg48: segment48 output tm2ioc: timer2 input / output p12 seg47 tm1ioc in/out p1dir2 p1plud2 seg47: segment47 output tm1ioc: timer1 input / output p13 seg46 tm3ioc in/out p1dir3 p1plud3 seg46: segment46 output tm3ioc: timer3 input / output p14 seg45 tm4ioc in/out p1dir4 p1plud4 seg45: segment45 output tm4ioc: timer4 input / output p15 seg44 tm7ioc in/out p1dir5 p1plud5 seg44: segment44 output tm7ioc: timer7 input / output buzzerb buzzerb: buzzer output p16 seg43 tm8ioc in/out p1dir6 p1plud6 seg43: segment43 output tm8ioc: timer8 input / output nbuzzerb nbuzzerb: buzzer inversion output p20 seg54 irq0 in/out p2dir0 p2plud0 seg54: segment54 output irq0: external interrupt0 acz0 acz0: zero-cross detection input p21 seg53 irq1 in/out p2dir1 p2plud1 seg53: segment53 output irq1: external interrupt1 acz1 acz1: zero-cross detection input p22 seg52 irq2 in/out p2dir2 p2plud2 seg52: segment52 output irq2: external interrupt2 p23 seg51 irq3 in/out p2dir3 p2plud3 seg51: segment51 output irq3: external interrupt3 p24 seg50 irq4 in/out p2dir4 p2plud4 seg50: segment50 output irq4: external interrupt4 p27 nrst in - - nrst: reset mode object microcontroller activation area pin setting register setting nrst atrst dmod p01 p02 mmod exmem flag
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e p30 seg42 sbo2b in/out p3dir0 p3plud0 seg42: segment42 output sbo2b: serial2 transmission data output txd2b txd2b: uart2 transmission data output p31 seg41 sbi2b in/out p3dir1 p3plud1 seg41: segment41 output sbi2b: serial2 reception data output rxd2b rxd2b: uart2 reception data input p32 seg40 sbt2b in/out p3dir2 p3plud2 seg40: segment40 output sbt2b: serial2 clock input / output p33 seg39 sbo4b in/out p3dir3 p3plud3 seg39: segment39 output sbo4b: serial4 transmission data output sda4b sda4b: iic4 data input / output p34 seg38 sbt4b in/out p3dir4 p3plud4 seg38: segment38 output sbt4b: serial4 clock input / output scl4b scl4b: iic4 clock input / output p35 seg37 sbi4b in/out p3dir5 p3plud5 seg37: segment37 output sbi4b:serial4 reception data output p36 seg36 in/out p3dir6 p3plud6 seg36: segment36 output p40 seg35 sbo3b in/out p4dir0 p4plud0 seg35: segment35 output sbo3b: serial3 transmission data output txd3b txd3b: uart3 transmission data output p41 seg34 sbi3b in/out p4dir1 p4plud1 seg34: segment34 output sbi3b: serial3 reception data output rxd3b rxd3b: uart3 reception data input p42 seg33 sbt3b in/out p4dir2 p4plud2 seg33: segment33 output sbt3b: serial3 clock input / output p43 seg32 sbo0b in/out p4dir3 p4plud3 seg32: segment32 output sbo0b: serial0 transmission data output txd0b txd0b: uart0 transmission data output p44 seg31 sbi0b in/out p4dir4 p4plud4 seg31: segment31 output sbi0b: serial0 reception data output rxd0b rxd0b: uart0 reception data input p45 seg30 sbt0b in/out p4dir5 p4plud5 seg30: segment30 output sbt0b: serial0 clock input / output p46 seg29 sda5b in/out p4dir6 p4plud6 seg29: segment29 output sda5b: iic5 data input / output p47 seg28 scl5b in/out p4dir7 p4plud7 seg28: segment28 output scl5b: iic5 clock input / output p50 seg20 key0 in/out p5dir0 p5plud0 seg20: segment20 output key0: key interrupt input0 d0 sbo0a d0: data input / output (bp0) sbo0a: serial0 transmission data output txd0a txd0a: uart0 reception data input p51 seg21 key1 in/out p5dir1 p5plud1 seg21: segment21 output key1: key interrupt input1 d1 sbi0a d1:data input / output (bp1) sbi0a: serial0 reception data output rxd0a rxd0a: uart0 transmission data output p52 seg22 key2 in/out p5dir2 p5plud2 seg22: segment22 output key2: key interrupt input2 d2 sbt0a d2: data input / output (bp2) sbt0a: serial0 clock input / output p53 seg23 key3 in/out p5dir3 p5plud3 seg23: segment23 output key3: key nterrupt input3 d3 buzze ra d3: data input / output (bp3) buzzera:buzzer output p54 seg24 key4 in/out p5dir4 p5plud4 seg24: segment24 output key4: key interrupt input4 d4 nbuzze ra d4:data input / output (bp4) nbuzzera: buzzer inversion output p55 seg25 key5 in/out p5dir5 p5plud5 seg25: segment25 output key5: key interrupt input5 d5 d5: data input / output (bp5) p56 seg26 key6 in/out p5dir6 p5plud6 seg26: segment26 output key6:key interrupt input6 d6 d6:data input / output (bp6) p57 seg27 key7 in/out p5dir7 p5plud7 seg27: segment27 output key7: key interrupt input7 d7 d7: data input / output (bp7) pins special functions i/o direction control pin control functions description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e p60 seg19 in/out p6dir0 p6plud0 seg19: segment19 output p61 seg18 da_b in/out p6dir1 p6plud1 seg18: segment18 output da_b: analog b output p62 seg17 a0 in/out p6dir2 p6plud2 seg17: segment17 output a0: address output (bp0) tm1iob tm1iob: timer1 input / output p63 seg16 a1 in/out p6dir3 p6plud3 seg16: segment16 output a1: address output (bp1) tm3iob tm3iob: timer3 input / output p64 seg15 a2 in/out p6dir4 p6plud4 seg15: segment15 output a2: address output (bp2) tm4iob tm4iob: timer4 input / output p65 seg14 a3 in/out p6dir5 p6plud5 seg14: segment14 output a3: address output (bp3) sbi4a sbi4a: serial4 reception data output p66 seg13 a4 in/out p6dir6 p6plud6 seg13: segment13 output a4: address output (bp4) sbo4a sda4a sbo4a: serial4 transmission data output sda4a: iic4 data input / output p67 seg12 a5 in/out p6dir7 p6plud7 seg12: segment12 output a5: address output (bp5) sbt4a scl4a sbt4a: serial4 clockinput / output scl4a: iic4 clock input / output p70 seg11 a6 in/out p7dir0 p7plud0 seg11: segment11 output a6: address output (bp6) sbo2a txd2a sbo2a: serial2 transmission data output txd2a: uart2 transmission data output p71 seg10 a7 in/out p7dir1 p7plud1 seg10: segment10 output a7: address output (bp7) sbi2a rxd2a sbi2a: serial2 reception data output rxd2a: uart2 reception data input p72 seg9 nwe in/out p7dir2 p7plud2 seg9: segment9 output nwe: write enable signal sbt2a sbt2a: serial2 clock input / output p73 sda5a nre in/out p7dir3 p7plud3 sda5a: iic5 data input / output nre: read enable signal seg8 seg8: segment8 output p74 scl5a ncs in/out p7dir4 p7plud4 scl5a: iic5 clock input / output ncs: chip selection signal seg7 seg7: segment7 output p75 txd1b sbo1b in/out p7dir5 p7plud5 txd1b: uart1 transmission data output sbo1b: serial1 transmission data output a8 seg6 a8: address output (bp8) seg6: segment6 output p76 rxd1b sbi1b in/out p7dir6 p7plud6 rxd1b: uart1 reception data input sbi1b: serial1 reception data output a9 seg5 a9: address output (bp9) seg5: segment5 output p77 sbt1b a10 in/out p7dir7 p7plud7 sbt1b: serial1 clock input / output a10: address output (bp10) seg4 seg4: segment4 output p80 tm9od0 sdo0 in/out p8dir0 p8plu0 tm9od0: timer9 output sdo0: timer synchronous output0 a11 seg3 a11: address output (bp11) seg3: segment3 output p81 tm9od1 sdo1 in/out p8dir1 p8plu1 tm9od1: timer9 output sdo1: timer synchronous output1 a12 seg2 a12: address output (bp12) seg2: segment2 output p82 tm9od2 sdo2 in/out p8dir2 p8plu2 tm9od2: timer9 output sdo2: timer synchronous output2 a13 seg1 a13: address output (bp13) seg1: segment1 output p83 tm9od3 sdo3 in/out p8dir3 p8plu3 tm9od3: timer9 output sdo3: timer synchronous output3 a14 seg0 a14: address output (bp14) seg0: segment0 output p84 tm9od4 sdo4 in/out p8dir4 p8plu4 tm9od4: timer9 output sdo4: timersynchronou soutput4 a15 com0 a15: address output (bp15) com0: lcd common output p85 tm9od5 sdo5 in/out p8dir5 p8plu5 tm9od5: timer9 output sdo5: timer synchronous output5 a16 com1 a16: address output (bp16) com1:lcd common output p86 sdo6 a17 in/out p8dir6 p8plu6 sdo6: timer synchronous output6 a17: address output (bp17) com2 com2:lcd common output p87 sdo7 a18 in/out p8dir7 p8plu7 sdo7: timer synchronous output7 a18: address output (bp18) com3 com3:lcd common output pins special functions i/o direction control pin control functions description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e p90 xi in p9dir0 p9plu0 xi: clock input pin p91 xo out p9dir1 p9plu1 xo: clock output pin p92 a19 v lc3 in/out p9dir2 p9plu2 a19: address output (bp19) v lc3 : lcd power supply p93 ndk v lc2 in/out p9dir3 p9plu3 ndk: data acknowledge signal v lc2 :lcd power supply p94 v lc1 da_c in/out p9dir4 p9plu4 v lc1 :lcd power supply da_c: analogc output p95 da_d in/out p9dir5 p9plu5 da_d: analogd output pa0 rmouta an0 tm0ioa in/out padir0 paplu0 rmouta:remote control carrier output an0: analog0 input tm0ioa: timer0 input / output pa1 tm1ioa an1 in/out padir1 paplu1 tm1ioa: timer1 input / output an1: analog1 input pa2 tm2ioa an2 in/out padir2 paplu2 tm2ioa: timer2 input / output an2: analog2 input pa3 tm3ioa an3 in/out padir3 paplu3 tm3ioa: timer3 input / output an3: analog3 input pa4 tm4ioa an4 in/out padir4 paplu4 tm4ioa: timer4 input / output an4: analog4 input pa5 tm7ioa an5 in/out padir5 paplu5 tm7ioa: timer7 input / output an5: analog5 input pa6 tm8ioa an6 in/out padir6 paplu6 tm8ioa: timer8 input / output an6: analog6 input pa7 tm9ioa an7 in/out padir7 paplu7 tm9ioa: timer9 input / output an7: analog7 input pb0 an8 in/out pbdir0 pbplu0 an8: analog8 input pb1 an9 in/out pbdir1 pbplu1 an9: analog9 input pb2 an10 in/out pbdir2 pbplu2 an10: analog10 input pb3 an11 in/out pbdir3 pbplu3 an11: analog11 input da1_ dout da1_dout out - - audio digital output da1_ aout da1_aout out - - audio analog output pins special functions i/o direction control pin control functions description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.3.3 pin functions table:1.3.2 pin functions name no i/o other function function description v ss v dd5 av dd av ss 15 18 93 96 - power connect pins supply 2.2 v to 5.5 v to v dd5 , 5.0 v to av dd and 0 v to v ss and av ss . v dd18 (capacity 1.8 v) 19 - capacity con- nect pins for internal power circuit output stability, connect at least one bypass capacitor of 1 uf or larger between v dd18 and v ss . v dd (capacity 3.3 v) 20 - capacity con- nect pins for internal power circuit output stability, connect at least one bypass capacitor of 1 uf or larger between v dd and v ss . (only flash version) osc1 osc2 16 17 input output clock input pins clock output pins connect these oscillation pins to ceramic or crystal ocsillators for high-frequency clock operation. if the clock is an external input, connect it to osc1 and leave osc2 open. the chip will not operate with an external clock when using either the stop or slow modes. xi xo 14 13 input output p90 p91 clock input pins clock output pins connect these oscillation pins to crystal oscillators for low-frequency clock operation. if the clock is an external input, connect it to xi and leave xo open. the chip will not operate with an exter- nal clock when using the stop mode. if these pins are not used, connect xi to v ss and leave xo open. nrst 12 input p27 reset pin [active low] this pin resets the chip when power is turned on, is allocated as p27 and contains an internal pull-up resistor (type. 50 k ?? . setting this pin low initialize the internal state of the device. thereafter, setting the input to high releases the reset. the hardware waits for the system clock to stabilize, then processes the reset interrupt. also, if ?0? is written to p27 and the reset is initiated by software, a low level will be output. the output has an n-channel open-drain configuration. if a capacitor is to be inserted between nrst and v ss , it is recom- mended that a discharge diode be placed between nrst and v dd5 . atrst 11 input auto reset setting pins 2 input ?h? to enable auto reset function and ?l? to dis- able this function p00 22 i/o rxd1a,sbi1a,tm7iob,led0 i/o port0 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the p0dir register. a pull-up /pull-down resistor for each bit can be selected individually by the p0plud register. a pull-up/down resistor connection for each port can be selected individually by the selud register. (how- ever, pull-up and pull-down resistors cannot be mixed.) direct led drive available at output. at reset, the input mode is selected and pull-up resistors are disabled (high impedance). p01 23 txd1a,sbo1a,tm8iob,led1 p02 24 sbt1a,tm9iob,led2 p03 25 rmoutb,tm0iob, tm2iob,led3 p04 26 led4,sbo3a,txd3a p05 27 led5,sbi3a,rxd3a p06 28 led6,sbt3a p07 29 led7,da_a
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e p10 35 i/o seg49,tm0ioc,rmoutc i/o port1 7-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the p1dir register. a pull-up /pull-down resistor for each bit can be selected individually by the p1plud register. a pull-up/down resistor connection for each port can be selected individually by the selud register. a pull- up/pull down can not be mixed. at reset, the input mode is selected and pull-up resistors are disabled (high impedance). p11 36 seg48,tm2ioc p12 37 seg47,tm1ioc p13 38 seg46,tm3ioc p14 39 seg45,tm4ioc p15 40 seg44,tm7ioc,buzzerb p16 41 seg43,tm8ioc,nbuzzerb p20 30 i/o seg54,irq0,acz0 i/o port2 5-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the p2dir register. a pull-up /pull-down resistor for each bit can be selected individually by the p2plud register. a pull-up/down resistor connection for each port can be selected individually by the selud register. (a pull-up/pull down can not be mixed.) at reset, the input mode is selected and pull-up resistors are disabled (high impedance) p21 31 seg53,irq1,acz1 p22 32 seg52,irq2 p23 33 seg51,irq3 p24 34 seg50,irq4 p27 12 input nrst i/o port2 port p27 has an n-channel open-drain configuration. when ?0? is written and the reset is initiated by soft- ware, a low level will be output. p30 42 i/o seg42,sbo2b,txd2b i/o port3 7-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the p3dir register. a pull-up /pull-down resistor for each bit can be selected individually by the p3plud register. a pull-up/down resistor connection for each port can be selected individually by the selud register. (a pull-up/pull down can not be mixed.) at reset, the input mode is selected and pull-up resistors are disabled (high impedance) p31 43 seg41,sbi2b,rxd2b p32 44 seg40,sbt2b p33 45 seg39,sbo4b,sda4b p34 46 seg38,sbt4b,scl4b p35 47 seg37,sbi4b p36 48 seg36 p40 49 i/o seg35,sbo3b,txd3b i/o port4 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the p4dir register. a pull-up /pull-down resistor for each bit can be selected individually by the p4plud register. a pull-up/down resistor connection for each port can be selected individually by the selud register. a pull- up/pull down can not be mixed. at reset, the input mode is selected and pull-up resistors are disabled (high impedance) p41 50 seg34,sbi3b,rxd3b p42 51 seg33,sbt3b p43 52 seg32,sbo0b,txd0b p44 53 seg31,sbi0b,rxd0b p45 54 seg30,sbt0b p46 55 seg29,sda5b p47 56 seg28,scl5b p50 64 i/o seg20,key0,d0,sbo0a, txd0a i/o port5 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the p5dir register. a pull-up /pull-down resistor for each bit can be selected individually by the p5plud register. a pull-up/down resistor connection for each port can be selected individually by the selud register. (a pull-up/pull down can not be mixed.) at reset, the input mode is selected and pull-up resistors are disabled (high impedance) p51 63 seg21,key1,d1,sbi0a, rxd0a p52 62 seg22,key2,d2,sbt0a p53 61 seg23,key3,d3,buzzera p54 60 seg24,key4,d4,nbuzzera p55 59 seg25,key5,d5 p56 58 seg26,key6,d6 p57 57 seg27,key7,d7 p60 65 i/o seg19 i/o port6 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the p6dir register. a pull-up /pull-down resistor for each bit can be selected individually by the p6plud register. a pull-up/down resistor connection for each port can be selected individually by the selud register. (a pull-up/pull down can not be mixed.) at reset, the input mode is selected and pull-up resistors are disabled (high impedance) p61 66 seg18,da_b p62 67 seg17,a0,tm1iob p63 68 seg16,a1,tm3iob p64 69 seg15,a2,tm4iob p65 70 seg14,a3,sbi4a p66 71 seg13,a4,sbo4a,sda4a p67 72 seg12,a5,sbt4a,scl4a name no i/o other function function description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e p70 73 i/o seg11,a6,sbo2a,txd2a i/o port7 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the p7dir register. a pull-up /pull-down resistor for each bit can be selected individually by the p7plud register. a pull-up/down resistor connection for each port can be selected individually by the selud register. (a pull-up/pull down can not be mixed.) at reset, the input mode is selected and pull-up resistors are disabled (high impedance) p71 74 seg10,a7,sbi2a,rxd2a p72 75 seg9,nwe,sbt2a p73 76 seg8,sda5a,nre p74 77 seg7,scl5a,ncs p75 78 seg6,txd1b,sbo1b,a8 p76 79 seg5,rxd1b,sbi1b,a9 p77 80 seg4,sbt1b,a10 p80 81 i/o tm9od0,sdo0,a11,seg3 i/o port8 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the p8dir register. a pull-up resistor for each bit can be selected individually by the p8plud register. at reset, the input mode is selected and pull-up resis- tors are disabled (high impedance) p81 82 tm9od1,sdo1,a12,seg2 p82 83 tm9od2,sdo2,a13,seg1 p83 84 tm9od3,sdo3,a14,seg0 p84 85 tm9od4,sdo4,a15,com0 p85 86 tm9od5,sdo5,a16,com1 p86 87 sdo6,a17,com2 p87 88 sdo7,a18,com3 p90 14 i/o xi i/o port9 7-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the p9dir register. a pull-up resistor for each bit can be selected individually by the p8plud register. at reset, the input mode is selected and pull-up resis- tors are disabled (high impedance) p91 13 xo p92 89 a19,v lc3 p93 90 ndk,v lc2 p94 91 da_c,v lc1 p95 92 da_d pa0 1 i/o rmouta,tm0ioa,an0 i/o porta 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the padir register. a pull-up resistor for each bit can be selected individually by the paplud register. at reset, the input mode is selected and pull-up resis- tors are disabled (high impedance) pa1 2 tm1ioa,an1 pa2 3 tm2ioa,an2 pa3 4 tm3ioa,an3 pa4 5 tm4ioa,an4 pa5 6 tm7ioa,an5 pa6 7 tm8ioa,an6 pa7 8 tm9ioa,an7 pb0 100 i/o an8 i/o portb 8-bit cmos tri-state i/o port. each bit can be set individually as either an input or output by the pbdir register. a pull-up resistor for each bit can be selected individually by the pbplud register. at reset, the input mode is selected and pull-up resis- tors are disabled (high impedance) pb1 99 an9 pb2 98 an10 pb3 97 an11 da1_dout da1_aout 94 95 i/o audio output pins special output pins for audio production function these output ?l? at reset. sbo0a 64 i/o p50,seg20,key0,d0 serial interface transmission data output pins for serial interface 0 to 4. the output configuration, either cmos push-pull or n- channel open-drain can be selected with the p0odc, p3odc, p4odc, p5odc, p6odc, p7odc registers. pull-up resistor can be selected by the p0plud, p3plud, p4plud, p5plud, p6plud and p7plud registers. select the output mode at the p0dir, p3dir, p4dir, p5dir, p6 dir and p7dir registers and serial data output mode by serial mode register 1 (sc0md1 to sc4md1). these can be used as normal i/o pins when the serial interface is not used. sbo0b 52 p43,seg32,txd0b transmission sbo1a 23 txd1a,tm8iob,led1,p01 data output pins sbo1b 78 txd1b,a8,seg6,p75 sbo2a 73 p70,seg11,a6,txd2a sbo2b 42 p30,seg42,txd2b sbo3a 26 p04,led4,txd3a sbo3b 49 p40,seg35,txd3b sbo4a 71 p66,seg13,a4,sda4a sbo4b 45 p33,seg39,sda4b name no i/o other function function description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e sbi0a 63 input p51,seg21,key1,d1 serial interface reception data output pins for serial interface 0 to 4. a pull-up resistor can be selected with the p0odc, p3odc, p4odc, p5odc, p6odc, p7odc registers. select the output mode at the p0dir, p3 dir, p4dir, p5dir, p6dir and p7dir registers and serial data output mode by serial mode register 1 (sc0md1 to sc4md1). these can be used as normal i/o pins when the serial interface is not used. sbi0b 53 p44,seg31,rxd0b reception sbi1a 22 rxd1a,tm7iob,led0,p00 data input pins sbi1b 79 rxd1b,a9,seg5,p76 sbi2a 74 p71,seg10,a7,rxd2a sbi2b 43 p31,seg41,rxd2b sbi3a 27 p05,led5,rxd3a sbi3b 50 p41,seg34,rxd3b sbi4a 70 p65,seg14,a3 sbi4b 47 p35,seg37 sbt0a 62 i/o p52,seg22,key2,d2 serial interface clock i/o pins for serial interface 0 to 4. the output configuration, either cmos push-pull or n- channel open-drain can be selected with the p0odc, p3odc, p4odc, p5odc, p6odc, p7odc registers. pull-up resistor can be selected by the p0plud, p3plud, p4plud, p5plud, p6plud and p7plud registers. select the clock i/o with the p0 dir, p3dir, p4dir, p5dir, p6dir and p7 dir registers and serial data output mode by serial mode register 1 (sc0md1 to sc4md1) according to the communication. these can be used as normal i/o pins when the serial interface is not used. sbt0b 54 p45,seg30 clock i/o pins sbt1a 24 tm9iob,led2,p02 sbt1b 80 a10,seg4,p77 sbt2a 75 p72,seg9,nwe sbt2b 44 p32,seg40 sbt3a 28 p06,led6 sbt3b 51 p42,seg33 sbt4a 72 p67,seg12,a5,scl4a sbt4b 46 p34,seg38,scl4b txd0a 64 output p50,seg20,key0,d0,sbo0a uart transmission data output pins in the serial interface0 to 3 in uart mode, this pin is configured as the transmission data output pin. the output configuration, either cmos push-pull or n- channel open-drain can be selected with the p0odc, p3odc, p4odc, p5odc, p7odc registers. pull-up resistor can be selected by the p0plud, p3plud, p4plud, p5plud and p7plud registers. select the output mode at the p0dir, p3 dir, p4dir, p5dir and p7dir registers and serial data output mode by serial mode register 1 (sc0md1 to sc3md1). these can be used as normal i/o pins when the serial interface is not used. txd0b 52 p43,seg32,sbo0b txd1a 23 sbo1a,tm8iob,led1,p01 txd1b 78 sbo1b,a8,seg6,p75 txd2a 73 p70,seg11,a6,sbo2a txd2b 42 p30,seg42,sbo2b txd3a 26 p04,led4,sbo3a txd3b 49 p40,seg35,sbo3b rxd0a 63 input p51,seg21,key1,d1,sbi0a uart reception data input pins in the serial interface0 to 3 in uart mode, this pin is configured as the reception data output pin. pull-up resistor can be selected by the p0plud, p3plud, p4plud, p5plud and p7plud registers. select the output mode at the p0dir, p3 dir, p4dir, p5dir and p7dir registers and serial data output mode by serial mode register 1 (sc0md1 to sc3md1). these can be used as normal i/o pins when the serial interface is not used. rxd0b 53 p44,seg31,sbi0b rxd1a 22 sbi1a,tm7iob,led0,p00 rxd1b 79 sbi1b,a9,seg5,p76 rxd2a 74 p71,seg10,a7,sbi2a rxd2b 43 p31,seg41,sbi2b rxd3a 27 p05,led5,sbi3a rxd3b 50 p41,seg34,sbi3b sda4a 71 i/o p66,seg13,a4,sbo4a iic data i/o pins in the serial interface4, 5 in iic mode, this pin is con- figured as the data input / output pin. for the output configuration, select n-channel open- drain with the p3odc, p4odc, p6odc and p7odc registers and pull-up resistors by the p3plud, p4plud, p6plud and p7plud registers. select the output mode at the p3dir, p4dir, p6dir and p7dir registers and serial data input / output mode by serial mode register 1 (sc4md1, sc5md1). these can be used as normal i/o pins when the serial interface is not used. sda4b 45 p33,seg39,sbo4b sda5a 76 nre,seg8,p73 sda5b 55 p46,seg29 name no i/o other function function description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e scl4a 72 i/o p67,seg12,a5,sbt4a iic clock i/o pins in the serial interface4, 5 in iic mode, this pin is con- figured as the clock input / output pin. for the output configuration, select n-channel open- drain with the p3odc, p4odc, p6odc and p7odc registers and pull-up resistors by the p3plud, p4plud, p6plud and p7plud registers. select the output mode at the p3dir, p4dir, p6dir and p7dir registers and serial data input / output mode by serial mode register 1 (sc4md1, sc5md1). these can be used as normal i/o pins when the serial interface is not used scl4b 46 p34,seg38,sbt4b scl5a 77 ncs,seg7,p74 scl5b 56 p47,seg28 tm0ioa 1 i/o rmouta,an0,pa0 timer i/o pins event counter clock input pin, timer output and pwm signal output pin for 8-bit timer 0 to 4. to use this pin as event clock input, configure this as input by p0dir register, p1dir register, p6dir regis- ter and padir register. in the input mode, pull-up resistors can be selected by the p0plud register, p1plud register, p6plud register and paplu regis- ter. for timer output, pwm signal output, select the spe- cial function pin by port 0 output mode register, port 1 output mode register, port 6 output mode register and port a output mode register ((p0omd, p1omd, p6omd and paomd), and set to the output mode at p0dir register, p1dir register and padir register. these can be used as normal i/o pins when the timer i/o is not used. tm0iob 25 rmoutb,tm2iob,led3,p03 tm0ioc 35 p10,seg49,rmoutc tm1ioa 2 an1,pa1 tm1iob 67 p62,seg17,a0 tm1ioc 37 p12,seg47 tm2ioa 3 an2,pa2 tm2iob 25 rmoutb,tm0iob,led3,p03 tm2ioc 36 p11,seg48 tm3ioa 4 an3,pa3 tm3iob 68 p63,seg16,a1 tm3ioc 38 p13,seg46 tm4ioa 5 an4,pa4 tm4iob 69 p64,seg15,a2 tm4ioc 39 p14,seg45 rmouta 1 i/o tm0ioa,an0,pa0 remote control output pin for remote control transmission with a car- rier signal. for remote control carrier output, select the special function pin by the port 0 output mode register, port 1 output mode register and port a output mode register (p0omd, p1omd and paomd), and set to the output mode by the p0dir register, p1dir register and padir register. at the same time, select remote control carrier output by the remote control carrier output register. these can be used as normal i/o pins when the buzzer output is not used. rmoutb 25 tm0iob,tm2iob,led3,p03 transmission rmoutc 35 p10,seg49,tm0ioc signal output pins buzzera 61 i/o p53,seg23,key3,d3 buzzer output piezoelectric buzzer driving pin. buzzer output avail- able to port1, port5. the driving frequency can be selected with the dlyctr register. to select buzzer output for porrt1, port5, select the special function pin by the port 1 output mode register and port 5 output mode register (p1omd and p5omd), and set to the output mode by the p1dir register and p5dir register. at the same time, select buzzer output by the oscilla- tion stabilization wait control register (dlyctr). these can be used as normal i/o pins when the buzzer output is not used. buzzerb 40 p15,seg44,tm7ioc nbuzzera 60 p54,seg24,key4,d4 nbuzzerb 41 p16,seg43,tm8ioc name no i/o other function function description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e tm7ioa 6 i/o an5,pa5 timer i/o pins event counter clock input pin, timer output and pwm signal output pin for 16-bit timer7 and 8. to use this pin as event clock input, configure this as input with the padir register. in the input mode, pull- up resistors can be selected by p0plu register, p1plu register and paplu register. for timer output, pwm signal output, select the spe- cial function pin by the port 0 output mode register, port 1 output mode register and port a output mode register (p0omd, p1omd and paomd), and set to the output mode at p0dir register, p1dir register and padir register. these can be used as normal i/o pins when not used as timer i/o pins. tm7iob 22 rxd1a,sbi1a,led0,p00 tm7ioc 40 p15,seg44,buzzerb tm8ioa 7 an6,pa6 tm8iob 23 txd1a,sbo1a,led1,p01 tm8ioc 41 p16,seg43,nbuzzerb tm9ioa 8 an7,pa7 tm9iob 24 sbt1a,led2,p02 tm9od0 81 output sdo0,a11,seg3,p80 timer output pins timer output and pwm signal output pin for 16-bit timer. to select timer output and pwm signal output, select the special function pin by the p8omd1 register, and set to the output mode at the p8dir register. these can be used as normal i/o pins when not used as timer i/o pins. tm9od1 82 sdo1,a12,seg2,p81 tm9od2 83 sdo2,a13,seg1,p82 tm9od3 84 sdo3,a14,seg0,p83 tm9od4 85 sdo4,a15,com0,p84 tm9od5 86 sdo5,a16,com1,p85 sdo0 81 output tm9od0,a11,seg3,p80 synchronous 8-bit synchronous output pins. synchronous output for each bit can be selected indi- vidually by the port 8 synchronous output control reg- ister (p8syo). set to the output mode by the p8dir register. these pins can be used as a normal i/o pins when not used for synchronous output pin. sdo1 82 tm9od1,a12,seg2,p81 output pins sdo2 83 tm9od2,a13,seg1,p82 sdo3 84 tm9od3,a14,seg0,p83 sdo4 85 tm9od4,a15,com0,p84 sdo5 86 tm9od5,a16,com1,p85 sdo6 87 a17,com2,p86 sdo7 88 a18,com3,p87 v ref+ 100 - + power supply for a/d converter reference power supply pins for the a/d converter. use this under the condition: 2.0 v ? v ref+ ? v dd5 an0 1 input rmouta,tm0ioa,pa0 analog input pins analog input pins for an 16-channel, 10-bit a/d con- verter. when not used for analog input, these pins can be used as normal input pins. an1 2 tm1ioa,pa1 an2 3 tm2ioa,pa2 an3 4 tm3ioa,pa3 an4 5 tm4ioa,pa4 an5 6 tm7ioa,pa5 an6 7 tm8ioa,pa6 an7 8 tm9ioa,pa7 an8 100 pb0 an9 99 pb1 an10 98 pb2 an11 97 pb3 da_a 29 output p07,led7 analog output pins analog output pins for an 4-channel, 8-bit a/d con- verter. when not used for analog output, these pins can be used as normal i/o pins. da_b 66 p61,seg18 da_c 91 v lc1 ,p94 da_d 92 p95 irq0 30 input p20,seg54 external interrupt external interrupt input pins. the valid edge for irq0 to 4 can be selected with the irqnicr register. irq1 has ac zero-cross detection function. irq1 can be set at both edges at pin voltage level. when not used for interrupts, these can be used as normal input pins. irq1 31 p21,seg53,acz1 input pins irq2 32 p22,seg52 irq3 33 p23,seg51 irq4 34 p24,seg50 name no i/o other function function description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e acz1 31 input p21,seg53,irq1 ac zero-cross detection input pins ac zero-cross detection input pin. ac zero-cross detection output ?h? when input level is mid-level and ?l? otherwise. acz input signal is connected to p20 input and irq0 interrupt circuit or p21 input and irq1 interrupt circuit. when not used for ac zero-cross detection, these can be used as normal input pins. acz0 30 p20,seg54,irq0 key0 64 input p50,seg20,d0,sbo0a, txd0a key interrupt input pins input pins for interrupt based on or result of pin inputs. these can be set to key input pins by 1-bit with the key interrupt control register (keyt3_1imd, keyt3_2imd) and by 2-bit with the key interrupt con- trol register (keyt3_1imd). when not used for key input, these pins can be used as normal i/o pins. key1 63 p51,seg21,d1,sbi0a, rxd0a key2 62 p52,seg22,d2,sbt0a key3 61 p53,seg23,d3,buzzera key4 60 p54,seg24,d4,nbuzzera key5 59 p55,seg25,d5 key6 58 p56,seg26,d6 key7 57 p57,seg27,d7 led0 22 i/o rxd1a,sbi1a,tm7iob,p00 led drive pins large current output pins. when not used for led output, these pins can be used as normal i/o pins. led1 23 txd1a,sbo1a,tm8iob,p01 led2 24 sbt1a,tm9iob,p02 led3 25 rmoutb,tm0iob,tm2iob, p03 led4 26 p04,sbo3a,txd3a led5 27 p05,sbi3a,rxd3a led6 28 p06,sbt3a led7 29 p07,da_a nwe 75 output p72,seg9,sbt2a write enable pins [active low] memory control signal used when the memory area is expanded to the external of this lsi. nwe is the strobe signal output for the write operation of the external memory and nre is the strobe signal output for the read operation of the external memory ncs is the chip selection signal outputs the external memory at the access. ndk is the acknowledge signal that indicates close of access to the external memory. nre 76 sda5a,seg8,p73 read enable pins [active low ncs 77 scl5a,seg7,p74 chip select pins [active low] ndk 90 input v lc2 ,p93 data acknowl- edge pins [active low] a0 67 output p62,seg17,tm1iob address pin a0-a19 is the address signal to the external memory. d0-d7 is the data i/o signal to the external memory. a1 68 p63,seg16,tm3iob a2 69 p64,seg15,tm4iob a3 70 p65,seg14,sbi4a a4 71 p66,seg13,sbo4a,sda4a a5 72 p67,seg12,sbt4a,scl4a a6 73 p70,seg11,sbo2a,txd2a a7 74 p71,seg10,sbi2a,rxd2a a8 78 txd1b,sbo1b,seg6,p75 a9 79 rxd1b,sbi1b,seg5,p76 a10 80 sbt1b,seg4,p77 a11 81 tm9od0,sdo0,seg3,p80 a12 82 tm9od1,sdo1,seg2,p81 a13 83 tm9od2,sdo2,seg1,p82 a14 84 tm9od3,sdo3,seg0,p83 a15 85 tm9od4,sdo4,com0,p84 a16 86 tm9od5,sdo5,com1,p85 a17 87 sdo6,com2,p86 a18 88 sdo7,com3,p87 a19 89 v lc3 ,p92 (continue to next page) name no i/o other function function description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e d0 64 i/o p50,seg20,key0,sbo0a, txd0a data pin (continued from previous page) d1 63 p51,seg21,key1,sbi0a, rxd0a d2 62 p52,seg22,key2,sbt0a d3 61 p53,seg23,key3,buzzera d4 60 p54,seg24,key4,nbuzzera d5 59 p55,seg25,key5 d6 58 p56,seg26,key6 d7 57 p57,seg27,key7 com0 85 output tm9od4,sdo4,a15,p84 lcd common output pins these pins output common signal of required timing for lcd display. connect to the common pins of lcd display panel. when the lcd functions are not used, these pins can be used as normal i/o port by the setting the lcd out- put control register lcctr0. com1 86 tm9od5,sdo5,a16,p85 com2 87 sdo6,a17,p86 com3 88 sdo7,a18,p87 v lc1 91 - sysclk,da_c,p94 lcd power sup- ply pins supply for lcd power. apply 5.5 v ? v lc1 ? v lc2 ? v lc3 ? 0 v. when the internal voltage divider resistor is used, v lc1 =v dd5 pin is selected as the reference voltage input pin. when lcd is not used, v lc1 to v lc3 can be used as normal i/o pins with the setting of lcd output control register0 (lcctr0). v lc2 90 ndk,p93 v lc3 89 a19,p92 seg0 84 output tm9od3,sdo3,a14,p83 lcd segment these pins output segment signal of required timing for lcd display. connect to the segment pins of the lcd display panel. when lcd display is turned off, v ss level is output. these pins can be used as normal i/o pins with the setting of lcd output control register lcctr1 to 7. seg can exchange segment pins and normal port by each bit. seg1 83 tm9od2,sdo2,a13,p82 output pinas seg2 82 tm9od1,sdo1,a12,p81 seg3 81 tm9od0,sdo0,a11,p80 seg4 80 sbt1b,a10,p77 seg5 79 rxd1b,sbi1b,a9,p76 seg6 78 txd1b,sbo1b,a8,p75 seg7 77 scl5a,ncs,p74 seg8 76 sda5a,nre,p73 seg9 75 p72,nwe,sbt2a seg10 74 p71,a7,sbi2a,rxd2a seg11 73 p70,a6,sbo2a,txd2a seg12 72 p67,a5,sbt4a,scl4a seg13 71 p66,a4,sbo4a,sda4a seg14 70 p65,a3,sbi4a seg15 69 p64,a2,tm4iob seg16 68 p63,a1,tm3iob seg17 67 p62,a0,tm1iob seg18 66 p61,da_b seg19 65 p60 seg20 64 p50,key0,d0,sbo0a,txd0a seg21 63 p51,key1,d1,sbi0a,rxd0a seg22 62 p52,key2,d2,sbt0a seg23 61 p53,key3,d3,buzzera seg24 60 p54,key4,d4,nbuzzera seg25 59 p55,key5,d5 seg26 58 p56,key6,d6 seg27 57 p57,key7,d7 seg28 56 p47,scl5b seg29 55 p46,sda5b seg30 54 p45,sbt0b seg31 53 p44,sbi0b,rxd0b (continue to next page) name no i/o other function function description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e seg32 52 p43,sbo0b,txd0b (continued from previous page) seg33 51 p42,sbt3b seg34 50 p41,sbi3b,rxd3b seg35 49 p40,sbo3b,txd3b seg36 48 p36 seg37 47 p35,sbi4b seg38 46 p34,sbt4b,scl4b seg39 45 p33,sbo4b,sda4b seg40 44 p32,sbt2b seg41 43 p31,sbi2b,rxd2b seg42 42 p30,sbo2b,txd2b seg43 41 p16,tm8ioc,nbuzzerb seg44 40 p15,tm7ioc,buzzerb seg45 39 p14,tm4ioc seg46 38 p13,tm3ioc seg47 37 p12,tm1ioc seg48 36 p11,tm2ioc seg49 35 p10,tm0ioc,rmoutc seg50 34 p24,irq4 seg51 33 p23,irq3 seg52 32 p22,irq2 seg53 31 p21,irq1,acz1 seg54 30 p20,irq0 mmod 10 input memory mode switch input pins set always to v ss . dmod 21 input mode switch input pins set always to v dd5 . name no i/o other function function description
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.4 block diagram 1.4.1 block diagram figure:1.4.1 block diagram * depending on the models. see [[1.1.2 product summary]] rom 508 kb ram 8 kb led1, tm8iob, sbo1a, txd1a, p01 led2, tm9iob, sbt1a, p02 led3, tm2iob, tm0iob, rmoutb, p03 txd3a, sbo3a, led4, p04 rxd3a, sbi3a, led5, p05 sbt3a, led6, p06 led0, tm7iob, sbi1a, rxd1a, p00 tm2ioc, seg48, p11 tm1ioc, seg47, p12 tm3ioc, seg46, p13 tm4ioc, seg45, p14 rmoutc, tm0ioc, seg49, p10 acz1, irq1, seg53, p21 irq2, seg52, p22 irq3, seg51, p23 irq4, seg50, p24 acz0, irq0, seg54, p20 rxd2b, sbi2b, seg41, p31 sbt2b, seg40, p32 sda4b, sbo4b, seg39, p33 scl4b, sbt4b, seg38, p34 scl4b, sbi4b, seg37, p35 txd2b, sbo2b, seg42, p30 txd3b, sbo3b, seg35, p40 rxd3b, sbi3b, seg34, p41 sbt3b, seg33, p42 txd0b, sbo0b, seg32, p43 sbt0b, seg30, p45 rxd0b, sbi0b, seg31, p44 d5, key5, seg25, p55 d6, key6, seg26, p56 d7, key7, seg27, p57 seg19, p60 da_b, seg18, p61 tm1iob, a0, seg17, p62 tm3iob, a1, seg16, p63 tm4iob, a2, seg15, p64 sbi4a, a3, seg14, p65 sda4a, sbo4a, a4, seg13, p66 scl4a, sbt4a, a5, seg12, p67 rxd2a, sbi2a, a7, seg10, p71 sbt2a, nwe, seg9, p72 seg8, nre, sda5a, p73 seg7, ncs, scl5a, p74 seg6, a8, sbo1b, txd1b, p75 seg5, a9, sbi1b, rxd1b, p76 seg4, a10, sbt1b, p77 txd2a, sbo2a, a6, seg11, p70 p86, sdo6, a17, com2 p85, tm9od5, sdo5, a16, com1 p84, tm9od4, sdo4, a15, com0 p83, tm9od3, sdo3, a14, seg0 p82, tm9od2, sdo2, a13, seg1 p81, tm9od1, sdo1, a12, seg2 p80, tm9od0, sdo0, a11, seg3 p87, sdo7, a18, com3 osc1 osc2 xi/p90 xo/p91 mmod v ref+ nrst, p27 pb3, an11 pb2, an10 pb1, an9 pb0, an8 pa6, tm8ioa, a8 pa5, tm7ioa, a7 pa4, tm4ioa, a4 pa3, tm3ioa, a3 pa2, tm2ioa, a2 pa1, tm1ioa, a1 pa7, tm9ioa, a9 pa0, rmouta, tm0ioa p95, da_d p94, da_c, v lc1 p93, ndkk, v lc2 p92, a19, v lc3 p91, xo p90, xi buzzerb, tm7ioc, seg44, p15 nbuzzerb, tm8ioc, seg43, p16 txd0a, sbo0a, d0, key0, seg20, p50 rxd0a, sbi0a, d1, key1, seg21, p51 sbt0a, d2, key2, seg22, p52 buzzera, d3, key3, seg23, p53 nbuzzera, d4, key4, seg24, p54 v dd5 v dd18 da_a, led7, p07 seg36, p36 sda5b, seg29, p46 scl5b, seg28, p47 dmod v ss av ss v dd av dd high-precision dac da1_aout da1_dout cpu mn101e audio reproduction time base timer6 pll d/a converter lcd low-speed oscillator circuit high-speed oscillator circuit 8-bit timer 0 8-bit timer 2 8-bit timer 3 8-bit timer a 16-bit timer 7 16-bit timer 8 16-bit timer 9 8-bit timer 1 external interrupt a/d converter port 1 port 0 port 2 port 3 port 5 port 6 port 7 serial interface 0 serial interface 1 serial interface 2 serial interface 3 serial interface 4 serial interface 5 watchdog timer buzzer data automatic transfer0, 1 port a port 9 port 8 port b port 4
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.5 electrical characteristics this lsi manual describes the standard specification. please ask our sales offices fo r the product specifications. model mn101e30 contents structure cmos integrated circuit application general purpose function cmos, 8-bit, single chip micro controller
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.5.1 absolute maxi mum ratings *2 *3 v ss = 0 v parameter symbol rating unit 1 power supply voltage v dd5 -0.3 to +7.0 v 2 capacity connection pin v dd18 -0.3 to +2.5 3*4 v dd -0.3 to +4.6 4 input clamp current (acz) i c -500 to +500 ? a 5 input pin voltage v i -0.3 to v dd5 + 0.3 v 6 output pin voltage v o -0.3 to v dd5 + 0.3 7 i/o pin voltage v io1 -0.3 to v dd5 + 0.3 8 peak power current p0 i ol1 (peak) 30 ma 9 other than p0 i ol2 (peak) 20 10 all pins i oh (peak) -10 11 average output current *1 p0 i ol1 (avg) 20 12 other than p0 i ol2 (avg) 15 13 all pins i oh (avg) -5 14 power dissipation p t 400 mw 15 operating ambient temperature t opr -40 to +85 ? c 16 storage temperature t stg -55 to +125 *1 applied to any 100 ms period. *2 connect approximate 1 ?? f capacitor between v dd18 /v dd power supply pin and the ground, and approximate 10-times capacitor connect to v dd18 /v dd between v dd5 power supply pin and the ground for the internal power supply stabiliza- tion. *3 the absolute maximum ratings are the limit values beyond which the lsi may be damaged. *4 applied only in flash version.
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.5.2 operating conditions .. use lcd power supply voltage with v lc1 ? v dd5 . .. v ss = 0 v ta = -40 ? c to +85 ? c parameter symbol condition rating unit min typ max power supply voltage *4 1 power supply voltage in not using pll v dd5-1 fosc ?? 20 mhz [double speed mode: fs ? 20 mhz] 2.2 5.5 v 2 in using pll v dd5-2 4.0 mhz ? fosc ? 10 mhz [multiplied by 2 to 10: fs ? 20 mhz] 2.2 5.5 3 v dd5-3 fx=32.768 khz [normal mode: fs ? fx/2] 2.2 5.5 4 voltage to maintain ram data v dd5-4 [during stop mode] 1.8 5.5 operating speed *5 5 instruction execution time t c1 v dd5 =2.2 v to 5.5 v 0.05 ? s 6 t c2 v dd5 =2.2 v to 5.5 v 61 *4 fosc: input clock frequency to osc1 pin. fx: input clock frequency to xi pin *5 t c1 : in the case of osc1 as cpu clock, or osc1 multiplied by pll as cpu clock. t c2 : in the case of xi as cpu clock.
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e .. connect external capacitors that suits the us ed pin. when crystal oscillator or ceramic oscillator is used, the frequency is change d depending on t he condenser rate . therefore, consult the manufacturer of the pin for the appropriate external capacitor. .. v ss = 0 v ta = -40 ? c to +85 ? c parameter symbol condition rating unit min typ max crystal oscillator 1 figure:1.5.1 [normal mode] 7 crystal frequency f xtal1 v dd5 = within the operation power supply voltage (refer to the reference value of power supply voltage 1 to 3.) 2.0 20 mhz 8 external capacitors c 11 10 pf 9 c 12 10 10 internal feedback resistor r f10 v dd5 =5.0 v 950 k ? crystal oscillator 2 figure:1.5.2 [slow mode] 11 crystal frequency f xtal2 v dd5 =2.2 v to 5.5 v 32.768 khz 12 external capacitors c 21 4 pf 13 c 22 4 14 internal feedback resistor r f20 v dd5 =5.0 v 6m ? figure:1.5.1 crystal oscillator 1 figure:1.5.2 crystal oscillator 2 osc1 fxtal1 r f10 osc2 c 12 c 1 1 instruction cycle becomes clock frequency divided by 1/2 built-in feedback resistor m n101e30n xi r f20 xo c 22 c2 1 instruction cycle becomes clock frequency divided by 1/2 built-in feedback resistor m n101e30n fxtal2
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e v dd5 = 2.2 v to 5.5 v v ss = 0 v ta = -40 ? c to +85 ? c parameter symbol condition rating unit min typ max external clock input 1 osc1 (osc2 is unconnected) 15 clock frequency f osc1 1.0 20.0 mhz 16 high level pulse width *6 t wh1 figure:1.5.3 22.5 ns 17 low level pulse width *6 t wl1 22.5 18 rising time *7 t wr1 figure:1.5.3 05.0 19 falling time *7 t wf1 05.0 external clock input 2 xi (xo is unconnected) 20 clock frequency f osc2 32.768 khz 21 high level pulse width *6 t wh2 figure:1.5.4 4.5 ? s 22 low level pulse width *6 t wl2 4.5 23 rising time *7 t wr2 figure:1.5.4 020 ns 24 falling time *7 t wf2 020 *6 the clock duty rate in the standard mode should be 45 % to 55 % *7 rising time and falling time differ depending on oscillation frequency. this is noted that the maximum value is a rough value, not a specified value. consult the oscillator manufacturer and perform matching tests for determining appropriate values.
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e figure:1.5.3 osc1 timing chart figure:1.5.4 xi timing chart t wh1 t wl1 0.9v dd5 t wf1 t wc1 t wr1 0.1v dd5 t wh2 t wl2 t wf2 t wc2 t wr2 0.9v dd 5 0.1v dd 5
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.5.3 dc characteristics v ss =0 v ta=-40 ? c to +85 ? c parameter symbol conditions rating unit min typ max power supply current *8 (normal mode: fs=fosc/2 slow mode: fs=fx/2) 1 power supply current i dd1 fosc=20 mhz [double-speed mode: fs=fosc] v dd5 =5 v (in not using pll) 4 (9) 8 (18) ma 2 i dd2 fosc=4 mhz [multiplied by 5: fs=20 mhz] v dd5 =5 v (in using pll) 4 (10) 8 (20) 3 i dd fosc=8 mhz [double-speed mode: fs=fosc] v dd5 =5 v (in not using pll) 1.5 (5) 3 (9) 4 i dd4 fosc=4 mhz [double-speed mode: fs=fosc] v dd5 =5 v (in not using pll) 1 (3) 2 (6) 5 i dd5 fx=32.768 mhz, [fs=fx/2] v dd5 =3 v ta=25 ? c 5 (60) 20 (120) ? a 6 i dd6 fx=32.768 mhz, [fs=fx/2] v dd5 =3 v ta=85 ? c 75 (200) 7 supply current during halt1 mode i dd7 fx=32.768 mhz v dd5 =3 v ta = 2 5 ? c 4 (6) 13 (18) 8 i dd8 fx=32.768 khz v dd5 =3 v ta = 8 5 ? c 70 (80) 9 supply current during stop mode i dd9 v dd5 =5 v ta=25 ? c 1 (2) 6 (7) 10 i dd10 v dd5 =5 v ta=85 ? c 60 (60)
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e *8 measured under condition without load. (pull-up / pull-down resistors are unconnected.) ? the supply current during operation, i dd1 to i dd4 are measured under the following conditions: after all i/o pins are set to input mode and the oscillation is set to , the mmod pin is at v ss level, the input pins are at v dd5 level, and a 20 mhz square wave of v dd5 and v ss amplitudes is input to the osc1 pin. ? the supply current during operation, i dd5 and i dd6 are measured under the following conditions: after all i/o pins are set to input mode and the oscillation is set to , the mmod pin is at v ss level, the input pins are at v dd5 level, and a 32.768 khz square wave of v dd5 and v ss amplitudes is input to the xi pin. ? the supply current during halt1 mode, i dd7 and i dd8 are measured under the following conditions: after all i/o pins are set to input mode and the os cillation is set to , the input pins are at v dd5 level, and an 32.768 khz square wave of v dd5 and v ss amplitudes is input to the xi pin. ? the supply current during stop mode, i dd9 and i dd10 are measured un der the following conditions: after the oscillation is set to , the mmod pin is at v ss level, the input pins are at v dd5 level, and the osc1 and xi pins are unconnected. ? the values in parentheses are for flash version.
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e v dd5 =2.2 v to 5.5 v v ss =0 v ta = - 4 0 ? c to +85 ? c parameter symbol conditions rating unit min typ max input pin 1 mmod, dmod, atrst 11 input high voltage v ih1 0.8v dd5 v dd v 12 input low voltage v il1 0 0.2v dd5 13 input leakage current i lk1 v in =0 v to v dd5 ?? 2 ? a i/o pin 2 p27 (nrst) 14 input high voltage v ih2 0.8v dd5 v dd5 v 15 input low voltage v il2 0 0.15v dd5 16 pull-up resistor r rh1 v dd5 =5.0v v in =v ss pull-up resistor on 10 50 100 k ? i/o pin 3 p10 to p16, p20 to p24, p30 to p36, p4 0 to p47, p50 to p57, p60 to p67, p70 to p77 17 input high voltage v ih3 0.8v dd5 v dd5 v 18 input low voltage v il3 0 0.2v dd5 19 input leakage current i lk2 v in =0 v to v dd5 ?? 2 ? a 20 pull-up resistor r rh2 v dd5 =5.0 v v in =v ss pull-up resistor on 10 50 100 k ? 21 pull-down resistor r rh1 v dd5 =5.0 v v in =v ss pull-down resistor on 10 50 100 22 output high voltage v oh1 v dd5 =5.0 v i oh =-0.5 ma 4.5 v 23 output low voltage v ol1 v dd5 =5.0 v i ol =1.0 ma 0.5
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e v dd5 =2.2 v to 5.5 v v ss =0 v ta=-40 ? c to +85 ? c parameter symbol conditions rating unit min typ max i/o pin 4 p80 to p87, p90 to p95, pa0 to pa7, pb0 to pb3 24 input high voltage v ih4 0.8v dd5 v dd5 v 25 input low voltage v il4 0 0.2v dd5 26 input leak current i lk3 v in =0 v to v dd5 ?? 2 ? a 27 pull-up resistor r rh 3 v dd5 =5.0 v v in =v ss pull-up resistor on 10 50 100 k ? 28 output high voltage v oh2 v dd5 =5.0 v i oh =0.5 ma 4.5 v 29 output low voltage v ol2 v dd5 =5.0 v i ol =1.0 ma 0.5 i/o pin 5 p00 to p07 30 input high voltage1 v ih5 0.8v dd5 v dd5 v 31 input low voltage1 v il5 0 0.2v dd5 32 input leak current i lk4 v in =0 v to v dd5 ?? 2 ? a 33 pull-up resistor r rh4 v dd5 =5.0 v v in =v ss pull-up resistor on 10 50 100 k ? 34 pull-down resistor r rl 2 v dd5 =5.0 v v in =v ss pull-down resistor on 10 50 100 35 output high voltage v oh3 v dd5 =5.0 v i oh =0.5 ma 4.5 v 36 output low voltage1 v ol3 v dd5 =5.0 v i ol =1.0 ma led output off 0.5 37 output low voltage2 v ol4 v dd5 =5.0 v i ol =15 ma led output on 1.0
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e v dd5 =2.2 v to 5.5 v v ss =0 v ta = - 4 0 ? c to +85 ? c parameter symbol conditions rating unit min typ max i/o pin 6 p20 (during used as acz) and p21 (during used as acz) are regulated at 5.0 v 38 input high voltage1 v dhh figure:1.5.5 4.5 v 39 input high voltage2 v dhl 1.5 40 input low voltage1 v dlh 3.5 41 input low voltage2 v dll 0.5 42 input clamp current i c3 v in > v dd5 , v in < 0 v ?? 500 ? a display output pin 1 com0 to com3 (at v lc1 , v ss voltage output) *9 43 output high voltage (in v lc1 voltage output) v ocomh v dd5 =v lc1 =5.0 v i com = -10 ? a 4.4 v 44 output low voltage (in v ss voltage output) v ocoml v dd5 =v lc1 =5.0 v i com =10 ? a 0.6 display output pin 2 seg0 to seg54 (at v lc1 , v ss voltage output) *10 45 output high voltage (in v lc1 voltage output) v osegh v dd5 =v lc1 =5.0 v i seg = -2 ? a 4.4 v 46 output low voltage (in v ss voltage output) v osegl v dd5 =v lc1 =5.0 v i seg =2 ? a 0.6 display power pin 1 v lc1 , v lc2 , v lc3 47 internal dividing resistor r vl1 ta = ? 25 ? c *11 (impedance between v lc1 and v ss ) 142.5 300 570 k ? 48 r vl2 15 30 60 *9 however, com0 to com3 are also used as p84 to p87. *10 however, seg0 to seg54 are also used as p10 to p16, p20 to p24, p30 to p36, p40 to p47, p50 to p57, p60 to p67, p70 to p77and p80 to 83. *11 summation of 3 resistors among v lc1 and v lc2 , v lc2 and v lc3 , v lc3 and v ss
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.5.4 a/c converter characteristics figure:1.5.5 operation of ac zero-cross detection circuit v dd5 =5.0 v v ss =0 v ta = - 4 0 ? c to +85 ? c parameter symbol conditions rating unit min typ max acz1 pin 1 rising time t rs figure:1.5.5 30 ? s 2 falling time t fs 30 trs ( input ) input 2 output 1 ( output ) v dd5 v dhl v dhh v dll v dlh v ss tfs
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.5.5 a/d converter characteristics .. the reference voltage input to v ref+ pin should be used on the condition of 2.0 v ?? v ref+ ?? v dd5 to avoid the malfunctions of microcomputer. .. v dd5 =5.0 v v ss =0 v ta=-40 ? c to +85 ? c parameter symbol conditions rating unit min typ max 1 resolution 10 bits 2 non-linearity error 1 v dd5 =5.0 v, v ss =0 v v ref+ =5.0 v t ad =800 ns *12 3 lsb 3 differential linearity error 1 3 4 zero transition voltage v dd5 =5.0 v, v ss =0 v v ref+ =5.0 v t ad =800 ns *12 -30 10 30 mv 5 full-scale transition voltage 4970 4990 5030 6 a/d conversion time t ad =800 ns *12 12.93 ? s 7 fx=32.768 khz t ad =15.2 ? s *12 427.25 8 sampling time t ad =800 ns *12 1.6 9 fx=32.768 khz t ad =15.2 ? s *12 30.52 10 reference voltage v ref+ note) 2.0 v dd5 v 11 analog input voltage v ss v ref+ 12 analog input leakage current when channel is off v adin =0 v to 5.0 v ? 2 ? a 13 reference voltage pin input leakage current when v ref+ is off v ss ?? v ref+ ?? v dd5 ? 5 14 ladder resistance r ladd v dd5 =5.0 v 15 40 80 k ? *12 t ad is a/d conversion clock cycle. the values of 2 to 5 are gu aranteed on the condition that v dd5 =v ref+ =5 v, v ss =0 v. note) the voltage difference between v ref+ and v ss should be set to more than 2 v.
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.5.6 d/a converter characteristics v dd5 =5.0 v v ss =0 v ta = 2 5 ? c parameter symbol conditions rating unit min typ max 1 resolution - - 8 bits 2 reference voltage low level d avss v ss - v 3 reference voltage high level d avdd - v dd5 4 zero scale output voltage v zs v dd5 =5.0 v, v ss =0 v d7 to d0=all "l" -0.05 0 0.05 5 full scale output voltage v fs v dd5 =5.0 v, v ss =0 v d7 to d0=all "h" 4.93 4.98 5.03 6 analog output resistance (minimum reference resistance) r oat 51015k ? 7 non-linearity error n le v dd5 =5.0 v, v ss =0 v - 2.0 3.0 lsb 8 differential non-linearity error d nle v dd5 =5.0 v, v ss =0 v - 2.0 3.0 9 settling time t set external capacitor cl=15 pf all bits are set to on or off -1.53.0 ? s
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.5.7 auto reset characteristics v dd5 =v rst to 5.5 v v ss =0 v ta = - 4 0 ? c to +85 ? c parameter symbol conditions rating unit min typ max power supply voltage 1 operation voltage v dd7 auto reset is used v rst 5.5 v power supply voltage 2 power supply detection level v rst 3.7 4.5 v 3 supply voltage change rate ? t/ ? v 250 ? s/v power supply current 4 auto reset power con- sumption i dd7 v dd5 =5 v 220 330 ? a
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.5.8 audio output characteristics figure:1.5.6 audio characteri stic measuring circuit (a) .. av dd and v dd5 should be at the same electric potential regardless of whether or not the audio production function is used. .. v dd5 =av dd =5.5 v v ss =0 v ta = - 4 0 ? c to +85 ? c parameter symbol conditions rating unit min typ max output pin 7 da1_aout 1 power supply voltage av dd av dd =v dd5 4.5 5.5 v 2 signal-to-noise ratio s/n av dd =5 v (note1) 80 88 db 3 dynamic range d.r. av dd =5 v (note1) 70 78 db 4 total harmonic distortion ratio thd+n av dd =5 v (note1) 0.16 0.26 % 5 output impedance r aout av dd =5 v 0.25 2.0 k ? output pin 8 da1_dout 6 output voltage high level v oh2 v dd5 =5.0 v i oh =-2 ma 4.5 v 7 output voltage low level v ol2 v dd5 =5.0 v i ol =2.0 ma 0.5 (note1) this is the value sampling 1khz sin wave at 20khz and recording with 16bit-pcm. (note2) h2,h3 and h4 are the output level at the measuring point on the audio charactoristic measuring curcuit(figure:1.5.6). amplifier circuit da1_aout av dd hpm measuring point av ss
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e figure:1.5.7 audio characteri stic measuring circuit (b) measuring point 2.2 k 100 pf 1 f 47 k 1 m 10 k - + - + - + 100 pf 1.5 k 47 k 1000 pf 2.7 k 10 k 1000 pf 1 k hpoutl hpoutr 93 96 + hpoutl hpoutr 220 f 100 ? 3.5 0.22 f 32 adacr adacl amplifier circuit hpm
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.5.9 flash eeprom program condition item symbol condition rating unit min typ max 1 programming voltage level v dd5-6 2.7 5.5 v 2 data retention period thold 10 years 3 programming guarantee number times e max 1000 times
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e 1.6 package dimension units: mm figure:1.6.1 package dimension (qfp100-p-1818b) .. the external dimensions of the package are su bject to change. before using this product, please obtain product specifications from the sales offices. .. sealing material: epoxy resin lead material : cu alloy lead surface processing : pd plating
mn101e30n/e30r/ef30r 8-bit single-chip microcontroller publication date: october 2015 pubno. 2163001-019e units: mm figure:1.6.2 package dimension (lqfp100) .. the external dimensions of the package are su bject to change. before using this product, please obtain product specifications from the sales offices. ..
request for your special attention and precautions in using the technical information and semiconductors described in this book (1) if any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) the technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. no license is granted in and to any intellectual property right or other right owned by panasonic corporation or any other company. therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) the products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. consult our sales staff in advance for information on the following applications: ? special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. it is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4) the products and product specifications described in this book are subject to change without notice for modification and/or im- provement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to make sure that the latest specifications satisfy your requirements. (5) when designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. otherwise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (esd, eos, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. when using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) this book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20100202

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